1. Field of the Invention
The present invention relates to a variable shift register and, more particularly, to a variable delay circuit for outputting delayed input data.
2. Description of the Prior Art
FIG. 1A is a block diagram showing a circuit for detecting a frame synchronization used in a communication system, using a conventional variable shift register. Referring to FIG. 1A, reference numerals 11-13 each denote variable shift registers, reference numeral 14 denotes a frame synchronization detecting circuit for receiving input or output signals of the variable shift registers 11-13 and detecting a frame synchronization of a signal, reference characters S1-S4 denote nodes showing inputs and/or outputs of each of the variable shift registers 11-13 and the frame synchronization detecting circuit and reference numeral 15 denotes a bit length setting circuit for receiving an input of a bit length setting signal for the variable shift registers and applying a bit length signal to each of the variable shift registers 11-13 for determining a delay time designated by each of the variable shift registers 11-13. In addition, the term "bit length" means the "length of a delay time" in this specification.
FIG. 1B shows a received data received by the circuit shown in FIG. 1A. Reference characters DATA0-DATA4 denote data containing necessary information out of those received data and reference characters F1-F4 denote frame synchronization patterns required for detecting a frame synchronization.
An operation is now described. The received data shown in FIG. 1B received by the circuit shown in FIG. 1A is inputted from the node S4 to the variable shift register 13 and then outputted from this circuit through the variable shift register 12 and the variable shift register 11. By appropriately setting the bit length of the variable shift registers 11-13 corresponding to a time interval between the frame synchronization patterns F1-F4 contained in the received data, the received data can be delayed by the time interval between the frame synchronization patterns F1-F4 at each of the variable shift registers 11-13. Therefore, at a certain time, the frame synchronization patterns F1, F2, F3 and F4 can be simultaneously detected at the nodes S1, S2, S3 and S4, respectively by the frame synchronization detecting circuit 14 and, as a result, it can be appreciated that the received data has been received in proper synchronization.
FIG. 2 is a system diagram showing the variable shift register used in a conventional frame synchronization detecting circuit, for example, shown in FIG. 1A. Referring to FIG. 2, reference characters R denote one-bit registers, reference numeral 1 denotes a bit length selecting circuit for determining a delay time to be achieved by this variable shift register, reference numeral 15 denotes a bit length setting circuit for applying bit length signals to the bit length setting circuit 1 to determine a delay time to be achieved by this variable shift register, reference characters S1-S8 denote switches controlled by the bit length selecting circuit 1. Reference character DI denotes input data, reference character DO denotes output data, reference characters a1, a2 and a3 denote bit length signals outputted from the bit length setting circuit 15 and applied to the bit length selecting circuit 1, and reference characters b1-b8 denote bit length switching signals outputted from the bit length selecting circuit 1 for activating the switches S1-S8.
Next, the operation of the thus structured shift register is described. When bit length data is set to the bit length setting circuit 15 to obtain a required delay time, the bit length signals a1, a2 and a3 are applied to the bit length selecting circuit 1 and, as a result, the bit length switching signals b1-b8 are outputted. Only one of the bit length switching signals b1-b8 is at "H" level, so that only one corresponding switch out of the switches S1-S8 is opened. Therefore, a word length of the shift register in FIG. 2 is determined.
Since the conventional variable shift register is thus structured, it has a problem that the number of registers used is increased causing larger power consumption when the delay time becomes long and the bit length to be set are caused to be long. Another problem was also involved that since the area on the semiconductor chip occupied by the register is as large as several to more than ten times the area occupied by the memory as far as one-bit information is concerned, obtaining an increased delay time or storage capacity in the conventional variable shift register entailed an increased in the occupied area.
Another well-known prior art of interest to the variable shift register of the present invention is now described and the difference between the prior art and the present invention and problems of the prior art are discussed in the following.
A variable bit length shift register comprising a RAM (Random Access Memory) is disclosed in Japanese Laying-Open Gazette No. 38939/1978 titled "Variable Bit Length Shift Register Device".
A variable shift register comprising a RAM and a variable counter in which a count number can be set is disclosed in Japanese Laying-Open Gazette No. 42529/1978 titled "Variable Shift Register".
A variable shift register comprising a RAM and a ring counter is disclosed in Japanese Laying-Open Gazette No. 42634/1978 titled "Variable Shift Register".
References of the above-mentioned three prior arts are obviously different from the present invention in that, each of the memory cells in the RAM of those three references does not comprise a circuit which is comprised in the present invention described in the following and which can perform a writing operation and a reading operation at the same time from and to different memory cells. Those three prior art references necessitate division of one cycle of a clock signal into a write cycle for controlling signals for writing and a read cycle for controlling signals for reading. Therefore, there were problems in which a control circuit becomes complicated and the length of one cycle of the clock signal becomes more than twice as long as an access time of the normal RAM, that is, an operating speed is limited.